1. Field of the Invention
The present disclosure generally relates to methods for fabricating integrated circuits, and, more specifically, to the formation of metallization layers including highly conductive metals into a dielectric material deposited on the surface of an integrated circuit.
2. Description of the Related Art
The ongoing trend in electronics towards more and more complex integrated circuits requires the dimensions of electronic devices to decrease, in order to achieve a higher and higher integration density.
In a typical electronic device included in an integrated circuit, transistors are the dominant circuit elements. Currently, several hundred millions of transistors may be provided in presently available complex integrated circuits, such as microprocessors, CPUs, storage chips and the like. It is then crucial that the typical dimensions of the transistors included in an integrated circuit are as small as possible, so as to enable a high integration density.
Due to the large number of circuit elements and the consequently complex layout of the integrated circuits, electrical connections to the individual circuit elements are generally not established within the same level on which the circuit elements are manufactured. In current integrated circuits, electrical connections are rather formed in one or more additional dedicated layers, also referred to as “wiring layers” or “metallization layers.”
Metallization layers may include metal-containing lines providing in-level electrical connection across a single layer. Furthermore, metallization layers may also include a plurality of inter-level connections, also referred to as vias. A via may be implemented by forming a hole connecting to predetermined metallization layers and by subsequently filling the hole with a metal having a high electrical conductivity.
The continuous shrinkage of feature sizes of circuit elements in modern integrated circuits causes the number of circuit elements for a given chip area to steadily increase, thereby allowing for an increase in packing density. As the packing density increases, the number of electrical interconnections is simultaneously required to increase in order to provide the desired circuit functionality. Thus, as the number of circuit elements per chip area becomes larger, the number of stacked metallization layers is to increase, thus calling for a reduction of the dimensions of metallization lines and vias.
The fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as mechanical, thermal and electrical reliability of a plurality of stacked metallization layers. As the complexity of integrated circuits advances, the need arises for conductive lines that can withstand moderately high current densities. In order to meet this ever more urgent need, semiconductor manufacturers are increasingly replacing the well-known metallization metal aluminum with metals that allow for higher current densities, so as to be able to reduce the dimensions of the interconnections and, consequently, the number of stacked metallization layers.
For example, copper has been found to be a viable candidate for replacing aluminum due to its higher resistance against electromigration and significantly lower electrical resistivity as compared to aluminum. Despite these advantages, copper also exhibits a number of drawbacks related to processing and handling in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD). Also, copper may not be effectively patterned by the usually employed anisotropic etch procedures. Furthermore, not only does copper rapidly diffuse into silicon, but it changes the electrical properties of silicon in such a way as to prevent transistors formed therein from functioning.
In order to overcome these obstacles, an effective technique for patterning copper in semiconductor devices has been recently developed called “damascene technique.”
In conventional deposition, a layer of metal and photoresist are deposited on a substrate, e.g., on a silicon wafer. Unwanted metal is then etched away with an appropriate chemical, leaving the desired pattern. Next, the spaces between the lines or vias are filled with an insulator, and finally the entire substrate surface is polished to remove excess insulator.
Damascene patterning involves the same number of steps, but reverses the order of deposition. A dielectric layer is first formed on the surface of the substrate including the integrated circuit or device. A pattern of trenches and holes is then formed in the dielectric layer by etching. The metal is then deposited after forming the pattern in the dielectric layer. The trenches filled with metal then rise to metal lines for the in-layer electrical connections, whereas the holes with the metal deposited therein will form the vias for inter-layer connection. After the deposition of the desired metal, the excess material deposited on areas outside of the trenches and vias has to be removed, which is currently accomplished by chemical mechanical polishing (CMP), possibly in combination with electrochemical etch techniques.
In both conventional and damascene patterning, the process is usually repeated many times to form the alternating layers of lines and vias which form the complete wiring system of a silicon chip.
The dielectric material in which the copper-based metal is embedded may advantageously comprise a so-called low-k material, that is, a material having a relative permittivity significantly lower than “conventional” dielectric materials, such as silicon dioxide, silicon nitride and the like. In general, the relative permittivity of a low-k material is equal to or less than 3.0. However, a low permittivity usually comes together with a significantly reduced mechanical strength and stability. Therefore, in typical damascene techniques for forming low-k metallization layers, a capping layer is provided that ensures the mechanical integrity of the low-k dielectric material by acting as a polish stop layer during the removal of the excess metal.
The process of filling copper or copper alloys into highly scaled openings, such as trenches or vias, having aspect ratios (depth/diameter) of approximately 5 or even more for sophisticated integrated circuits, is an extremely challenging task for process engineers.
As previously noted, copper and its respective alloys cannot effectively be deposited by chemical or physical vapor deposition. Hence, copper-based metals are typically deposited by electrochemical techniques, such as electroless plating or electroplating. Although electrochemical techniques for depositing copper are well established in the field of manufacturing integrated circuit boards, completely new deposition techniques have been developed for the formation of copper-based metallization layers in accordance with the damascene technique. In particular, deposition processes are required in which trenches and vias are filled substantially from bottom to top with a minimum number of defects, such as voids in the metal filling the trenches and vias.
With reference to FIGS. 1a-1d, a typical conventional process flow will now be described in more detail so as to more clearly demonstrate the problems involved in forming highly scaled copper lines in a dielectric material.
FIG. 1a schematically shows a cross-sectional view of a semiconductor device 100 comprising a substrate 101, which may be provided in the form of a bulk silicon substrate, an SOI (silicon-on-insulator) substrate and the like. The substrate 101 may also represent a device layer having formed therein individual circuit elements, such as transistors, capacitors, lines, contact portions and the like. For convenience, any such circuit elements are not shown in FIG. 1a. 
The semiconductor device 100 further comprises a dielectric layer 120 formed above the substrate 101. The dielectric layer 120 may represent a dielectric material enclosing the individual circuit elements. The dielectric layer 120 may also represent a portion of a lower-lying metallization layer, in which any metal-filled vias (not shown) may be embedded.
Depending on the specific design of the semiconductor device 100, the layer 120 may be comprised of a conventional dielectric material, such as silicon dioxide or silicon nitride, or may comprise a low-k dielectric material, such as, for instance, hydrogen-enriched silicon oxycarbide (SiCOH). Although not shown in the figures, the dielectric layer 120 can also represent a stack of insulating layers, wherein one or more than one metallization layer is formed. The stack may be comprised of an alternation of oxide layers, low-k material layers, capping layers, etc. The layers in the stack may be arranged depending on the structural and functional requirements of the semiconductor device 100.
FIG. 1a shows that the dielectric layer 120 right after deposition is a continuous film, free of voids or apertures. Subsequently, as shown in FIG. 1b, an etch process 181 may be carried out on the semiconductor device 100 in order to form apertures 170 in the dielectric layer 120. The apertures 170 are in general formed in predetermined positions, for example, by using an appropriately patterned resist mask (not shown) during the etch process 181.
The aperture 170 is shown in FIG. 1b as a hole or trench exposing a surface portion of the semiconductor substrate 101. However, the aperture 170 may extend by a smaller length than the total thickness of the dielectric layer 120. For example, the aperture 170 may extend through the dielectric layer 120 to a sufficient depth to expose a given metallization layer. Usually, the aperture 170 has a high aspect ratio, i.e., a high ratio of depth to length. In FIG. 1b, the depth and length of the aperture 170 are the dimensions of the trench along the horizontal and the vertical directions, respectively.
FIG. 1c schematically shows the semiconductor device 100 in a stage of the process flow following that shown in FIG. 1b. FIG. 1c shows the semiconductor device 100 after a metal film 140 has been deposited on its surface. If the metal film 140 comprises copper or a copper alloy, deposition may have been performed by electrochemical techniques. A conductive barrier layer 144 may have been formed on the surface of the dielectric layer 120 prior to the deposition of the metal film 140. The conductive barrier layer 144 has mainly the tasks of preventing metals, such as copper, from diffusing into the dielectric layer 120 and increasing adhesion of the metal onto the device surface.
During a typical deposition of a metal layer 140 by electroplating, the composition and the kinetics within an electrolyte bath are controlled so as to yield a highly non-conformal deposition behavior. In this manner, the metal, e.g., copper or a copper alloy, may be deposited from bottom to top within the aperture 170. For an aperture 170 having a high aspect ratio, even slight overhangs at the aperture edge 170e may lead to the creation of defects, such as voids 140v, within the aperture 170. Defects in the portion of the metal layer 140 filling the aperture 170 are undesirable, since they may cause concerns regarding the reliability of the metal-filled aperture 170.
FIG. 1d schematically shows the semiconductor device 100 with the excess material of the barrier layer 144 and the metal layer 140 removed. Removal of the excess material may be accomplished, as previously explained, at least partially by chemical mechanical polishing, during which a capping layer (not shown) may act as a stop layer. During the process of polishing the surface of the semiconductor device 100, a portion of the insulating layer 120 may also be etched.
Due to the voids 140v, the reliability of metallization layers is significantly affected. This is due to the fact that the corresponding line or via resulting from the metal-filled aperture 170 may have a reduced conductivity and may also exhibit increased current or temperature-induced material transport, i.e., electromigration, at elevated current densities as are typically encountered in highly scaled devices.
A solution to the problem of filling apertures having a high aspect ratio with a metal has been proposed in U.S. Pat. No. 8,101,524. The proposed method consists of performing a first etch process in the presence of a mask in order to form apertures in the insulating layer, removing the mask and performing a second etch process before depositing the metal in the apertures. The second etch process, typically consisting of a plasma-based etch, is performed in order to round the corners of the edges of the apertures formed by means of the first etch process. Whereas the first etch process is strongly anisotropic, a reduced anisotropic character may cause the second etch process to promote the desired effect of corner-rounding.
This method is not always satisfactory, since plasma etch may cause undesired effects, besides that of corner rounding. For example, a second plasma etch performed after forming the apertures may undesirably damage surface portions of the semiconductor device exposed through the apertures. This problem may, for example, arise when the apertures expose sensitive portions of the semiconductor substrate in and on top of which circuit elements are formed. In this case, a second plasma etch may erode portions of the substrate surface exposed through the aperture, thereby potentially causing damages to some circuit elements.
In view of the situation described above, there exists a need for an improved technique which allows one to solve or at least reduce the effects of one or more problems identified above.